Amarx Search, Inc. - amarx.com Direct Hire - Full Time position in NJ, Camden
Position ID: 2606An excellent position with a large defense technology company delivering innovative mission solutions * Senior ASIC-FPGA VHDL Design Engineer * Please apply ONLY if you have a BSEE and an active Secret Clearance United States Citizenship is required due to government contract requirement; we are unable to sponsor at this time. We can ONLY consider your application if you have:
1: BSEE, MSEE Preferred.
2: Proficiency in VHDL is a must
3: 5+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
4: Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
5: Proficient with CDC, RDC. Formal EDA.
6: Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado
7: Strong logic/board debug, and analytical skills.
8: Experience with project leadership and EVM
9: Excellent written, verbal, and presentation skills.
10: Active SECRET ClearanceReporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. This person will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.
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The company has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite: Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).
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This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.DESIRED (not required) SKILLS:
:: Proficiency in C++ (OOP)
:: Proficiency in Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
:: Knowledge of PCIe, NVMe, USB protocols
:: Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).Duties and Responsibilities
== Responsible for deriving engineering specifications from system requirements and developing detailed architecture
== Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
== Generate test plans
== Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
== Silicon/FPGA bring up, characterization and production ramp/support/collateralPlease send resume to apply@amarx.com - Amarx Search, Inc. - amarx.com Amarx Search, Inc. - amarx.com